Large Rapid-Prototyping Systems comprising several FPGAs become more and more the tool at hand to verify complete hardware systems at an early stage of development for first time success. Although hardware capability is growing rapidly the appropriate software tools are lacking in mapping performance and quality. It is especially difficult to meet certain real-time constraints when a design is distributed among several FPGAs. We propose a macro-based partitioning methodology that significantly improves turnaround times and leads to very compact hardware realizations. We demonstrate the benefits of our approach for a real-time video processing application. In additon, compilation time and hardware resources could be reduced by 35% and 45%, respectively.