This paper presents methods to add efficient cryptographic support to low-performance embedded processors with embedded networks (e.g. sensor networks). Software thread integration (STI) is used to create efficient threads which can perform cryptographic operations during time-slice (TDMA) communication, eliminating most context-switching overhead. The AvrX kernel is enhanced to automatically select the most efficient threads based upon available work, saving processor cycles and power. The results show that an STI-based implementation enables communication at higher rates while also performing more cryptographic work compared with traditional ISR (interrupt service routine) or busy-wait schemes. Significant performance improvements are found for both the RC4 and RC5 ciphers. First, STI enables cryptographic processing to occur during communication at a bit rate of f{cpu}/8, which is not possible with an ISR approach. Second, cryptographic throughput at lower communication rates increases by up to 200% for both RC4 and RC5.