Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit

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http://doi.ieeecomputersociety.org/10.1109/RTTAS.2004.1317287

10th IEEE Real-Time and Embedded Tech ...

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	Premysl Sucha, Zdenek Pohl, Zdenek Hanz?lek, "Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit," Real-Time and Embedded Technology and Applications Symposium, IEEE, pp. 404, 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'04), 2004.

	BibTex	x
	@article{ 10.1109/RTTAS.2004.1317287, author = {Premysl Sucha and Zdenek Pohl and Zdenek Hanz?lek}, title = {Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit}, journal ={Real-Time and Embedded Technology and Applications Symposium, IEEE}, volume = {0}, year = {2004}, issn = {1080-1812}, pages = {404}, doi = {http://doi.ieeecomputersociety.org/10.1109/RTTAS.2004.1317287}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Real-Time and Embedded Technology and Applications Symposium, IEEE TI - Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit SN - 1080-1812 SP EP A1 - Premysl Sucha, A1 - Zdenek Pohl, A1 - Zdenek Hanz?lek, PY - 2004 KW - Cyclic scheduling KW - monoprocessor KW - iterative algorithms KW - integer linear programming KW - FPGA VL - 0 JA - Real-Time and Embedded Technology and Applications Symposium, IEEE ER -

Premysl Sucha, Czech Technical University in Prague

Zdenek Pohl, Institute of Information Theory and Automation

Zdenek Hanz?lek, Czech Technical University in Prague

This paper presents a scheduling technique for a library of arithmetic logarithmic modules for FPGA illustrated on a RLS filter for active noise cancellation. The problem under assumption is to find an optimal periodic cyclic schedule satisfying the timing constraints. The approach is based on a transformation to monoprocessor cyclic scheduling with precedence delays. We prove that this problem is NP-hard and we suggest a solution based on Integer Linear Programming that allows to minimize completion time. Finally experimental results of optimized RLS filter are shown.

Index Terms:

Cyclic scheduling, monoprocessor, iterative algorithms, integer linear programming, FPGA

Citation:

Premysl Sucha, Zdenek Pohl, Zdenek Hanz?lek, "Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit," rtas, pp.404, 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'04), 2004

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