The Limits of Speculative Trace Reuse on Deeply Pipelined Processors

S?o Paulo, SP - Brazil November 10-November 12

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http://doi.ieeecomputersociety.org/10.1109/CAHPC.2003.1250319

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	Maurício L. Pilla, Amarildo T. da Costa, Felipe M. G. França, Bruce R. Childers, Mary Lou Soffa, "The Limits of Speculative Trace Reuse on Deeply Pipelined Processors," Computer Architecture and High Performance Computing, Symposium on, pp. 36, 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'03), 2003.

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	@article{ 10.1109/CAHPC.2003.1250319, author = {Maurício L. Pilla and Amarildo T. da Costa and Felipe M. G. França and Bruce R. Childers and Mary Lou Soffa}, title = {The Limits of Speculative Trace Reuse on Deeply Pipelined Processors}, journal ={Computer Architecture and High Performance Computing, Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-2046-4}, pages = {36}, doi = {http://doi.ieeecomputersociety.org/10.1109/CAHPC.2003.1250319}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Architecture and High Performance Computing, Symposium on TI - The Limits of Speculative Trace Reuse on Deeply Pipelined Processors SN - 0-7695-2046-4 SP EP A1 - Maurício L. Pilla, A1 - Amarildo T. da Costa, A1 - Felipe M. G. França, A1 - Bruce R. Childers, A1 - Mary Lou Soffa, PY - 2003 KW - null VL - 0 JA - Computer Architecture and High Performance Computing, Symposium on ER -

Maurício L. Pilla, UFRGS

Amarildo T. da Costa, IME

Felipe M. G. França, UFRJ

Bruce R. Childers, University of Pittsburgh

Mary Lou Soffa, University of Pittsburgh

Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ready by the time the reuse test is done. For these cases, we developed a new technique called Reuse through Speculation on Traces (RST), where trace inputs may be predicted. This paper studies the limits of RST for modern processors with deep pipelines, as well as the effects of constraining resources on performance.We show that our approach reuses more traces than the non-speculative trace reuse technique, with speedups of 43% over a non-speculative trace reuse and 57% when memory accesses are reused.

Citation:

Maurício L. Pilla, Amarildo T. da Costa, Felipe M. G. França, Bruce R. Childers, Mary Lou Soffa, "The Limits of Speculative Trace Reuse on Deeply Pipelined Processors," sbac-pad, pp.36, 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'03), 2003

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