This paper presents T&D-Bench - Teaching and Design Workbench, a software infrastructure for modeling and simulation of state-of-the-art processors. It combines features that simplify and accelerate the processor design process without restricting the designer possibilities, thus representing a good trade-off for educational and research purposes that is not found in other environments. In T&D-Bench, a new model is constructed by the designer using a script language to define micro-architecture, instruction set, and timing aspects of the processor. These scripts can be produced by a graphical front-end, and a Java simulator targeted at the modeled processor is automatically built from the scripts. This approach can fit well the requirements imposed by the educational environment. Fine-tuning adjustments or the description of more complex processor mechanisms can be achieved by means of modifications in selected parts of the software infrastructure.