A heterogeneous environment for hardware/software cosimulation is described. This environment permits a portion of an application's subsystems to be simulated using reconfigurable hardware while the remainder of the subsystems are simulated using software. An Aptix FPCB populated with Xilinx FPGAs serves as the hardware simulation platform while an IBM-compatible PC serves as the software simulation platform. The two platforms are connected using an Altera reconfigurable logic board which allows the development of a high-speed interface for communication. This paper focuses on the difficulties associated with designing and interfacing simulation entities in this heterogeneous environment. Strategies for designing hardware and software simulation entities are introduced. These strategies reduce the impact of size and performance constraints imposed by the cosimulation environment while addressing the issues of time management and synchronization. A simple queueing application is used to illustrate a design methodology which incorporates these design strategies.