VHDL is one of the most important and widely used hardware description languages at this time. Applications written in VHDL are increasing in size and complexity, which prompts the use of parallel algorithms to obtain acceptable simulation performance. We have investigated the use of an optimistic distributed algorithm with VHDL simulation. Optimistic simulation algorithms have been shown to deliver the highest performance of the currently available simulation strategies. It is however a difficult algorithm to implement, especially for VHDL which has all the characteristics of a high level programming language. With our simulation environment, ADVISE, we obtain speedups of around four for a medium-sized benchmark. The amount of speedup depends on the type of multi-processor architecture used, partitioning algorithm, and optimizations. Further optimization of the simulation and partitioning algorithms within ADVISE, the use of more advanced compilation strategies, and larger benchmarks should lead to higher speedups, which makes it worthwhile to investigate this approach further.