loading...
Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation
Seattle, WA April 22-April 26
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SIMSYM.2001.92211534th Annual Simulation Symposium (SS01)
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Bradley L. Noble, Southern Illinois University, Edwardsville
J. Cris Wade, Southern Illinois University, Edwardsville
Roger D. Chamberlain, Washington University
Abstract: VLSI logic simulation is an application area in which execution time improvements can have direct economic benefits. Here, we investigate the use of parallel simulation techniques to improve the performance of VLSI logic simulation, including the often neglected issue of sensitivity to variations in the simulation workload. Performance predictions are presented for the use of speculative computation in synchronous discrete-event simulation of VLSI systems.
Citation:
Bradley L. Noble, J. Cris Wade, Roger D. Chamberlain, "Performance Predictions for Speculative, Synchronous, VLSI Logic Simulation," ss, pp.0056, 34th Annual Simulation Symposium (SS01), 2001
Usage of this product signifies your acceptance of the Terms of Use.