Embedded DSP applications require large amount of high performance memory. Today's DSP systems typically have more than a megabit of on-chip memory, as compared to less than a hundred kilo-bits a few years ago. Memory performance can easily become a bottleneck in the system performance. This problem is compounded by the increasing interconnect delay factor at sub-micron technology. A high performance DSP core cannot alone guarantee a high performance system. In this paper, we address the challenges encountered in a high performance embedded DSP based design. We describe performance enhancing techniques ranging from careful physical placement, and logic design to optimal repeater insertion and buffering schemes. A methodology that efficiently addresses the interconnect effects is presented.