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An Upper Bound for 3D Slicing Floorplans
Bangalore, India January 07-January 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994982ASP-DAC/VLSI Design 2002
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Silke Salewski, Erich Barke, "An Upper Bound for 3D Slicing Floorplans," VLSI Design, International Conference on, pp. 567, ASP-DAC/VLSI Design 2002, 2002.
 
 
BibTex
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@article{ 10.1109/ASPDAC.2002.994982,
author = {Silke Salewski and Erich Barke},
title = {An Upper Bound for 3D Slicing Floorplans},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2002},
isbn = {0-7695-1441-3},
pages = {567},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994982},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - An Upper Bound for 3D Slicing Floorplans
SN - 0-7695-1441-3
SP
EP
A1 - Silke Salewski,
A1 - Erich Barke,
PY - 2002
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Silke Salewski, University of Hannover
Erich Barke, University of Hannover
As the impact of interconnect on IC performance and chip area in deep submicron design increases, research activities on technologies for three-dimensional integrated circuits intensify. Nevertheless, there is not much work done on the automation of 3D-layout design. In this paper we survey slicing structures for 3D floorplans. We present an upper bound for the volume of such floorplans, which shows the usability of slicing structures for three-dimensional floorplanning.
Citation:
Silke Salewski, Erich Barke, "An Upper Bound for 3D Slicing Floorplans," vlsid, pp.567, ASP-DAC/VLSI Design 2002, 2002
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