Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing

Bangalore, India January 07-January 11

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http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994986

ASP-DAC/VLSI Design 2002

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	Christoph Albrecht, Andrew B. Kahng, Ion Mandoiu, Alexander Zelikovsky, "Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing," VLSI Design, International Conference on, pp. 580, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994986, author = {Christoph Albrecht and Andrew B. Kahng and Ion Mandoiu and Alexander Zelikovsky}, title = {Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {580}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994986}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing SN - 0-7695-1441-3 SP EP A1 - Christoph Albrecht, A1 - Andrew B. Kahng, A1 - Ion Mandoiu, A1 - Alexander Zelikovsky, PY - 2002 VL - 0 JA - VLSI Design, International Conference on ER -

Christoph Albrecht, University of Bonn

Andrew B. Kahng, University of California at San Diego

Ion Mandoiu, University of California at San Diego

Alexander Zelikovsky, Georgia State University

We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good multi-commodity flow based algorithm that finds a global routing minimizing routing area (wirelength and number of buffers) subject to given constraints on buffer/wire congestion and sink delays. This permits detailed floorplan evaluation, i.e., computing the tradeoff curve between routing area and wire/buffer congestion under any combination of delay and capacity constraints.Our algorithm (1) enforces maximum source/buffer wireloads; (2) enforces wire and buffer congestion constraints by taking into account routing channel capacities and buffer site locations; (3) enforces individual sink delay constraints; (4) performs buffer/wire sizing and layer assignment; and (5) integrates pin assignment with virtually no increase in runtime. Preliminary experiments show that near-optimal results are obtained with a practical runtime.

Citation:

Christoph Albrecht, Andrew B. Kahng, Ion Mandoiu, Alexander Zelikovsky, "Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing," vlsid, pp.580, ASP-DAC/VLSI Design 2002, 2002

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