IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current drawn from the power supply after the application of a test vector exceeds a threshold value. A CMOS circuit only consumes leakage power after the switching transients settle down, and a large quiescent power-line current indicates a defective chip. With device counts in system chips crossing into millions, the leakage power is no more insignificant, making IDDQ tests unsafe. Yet, IDDQ tests are invaluable since they can catch faults that are not testable using voltage testing. In this paper, we propose a solution to make IDDQ testing practical for large system chips. Our technique is based on chip partitioning and scheduling the testing of partitions so that IDDQ testing can be safely practiced. We formulate partitioning as a constrained optimization problem and propose two algorithms for partitioning. The objective function for the optimization problem is the test execution time. We present experimental results to illustrate our methodology.