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India-Building the Tall, Thin VLSI Engineer
New Delhi, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.118310216th International Conference on VLSI ...
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Rajeev Madhavan, "India-Building the Tall, Thin VLSI Engineer," VLSI Design, International Conference on, pp. 5, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183102,
author = {Rajeev Madhavan},
title = {India-Building the Tall, Thin VLSI Engineer},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {5},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183102},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - India-Building the Tall, Thin VLSI Engineer
SN - 1063-9667
SP
EP
A1 - Rajeev Madhavan,
PY - 2003
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Rajeev Madhavan, Magma Design Automation
With logical and physical design melding together, an opportunity to build a new type of engineer is emerging rapidly. Powerful tools are enabling any engineer to deliver a high quality of results once possible for only a seasoned designer. These leading-edge tools and technologies are changing the boundaries between logic and physical design, between system and chip design, and between novice and seasoned designer. Given the right tools, computer scientists and electronics engineers both can play pivotal roles in enabling the transition to nanometer system-on- chip designs. And with unparalleled technical prowess and aptitude to adapt, India is in the best position to lead this evolution.
Citation:
Rajeev Madhavan, "India-Building the Tall, Thin VLSI Engineer," vlsid, pp.5, 16th International Conference on VLSI Design, 2003
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