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A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs
New Delhi, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.118312016th International Conference on VLSI ...
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Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri, "A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs," VLSI Design, International Conference on, pp. 91, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183120,
author = {Manish Handa and Rajesh Radhakrishnan and Madhubanti Mukherjee and Ranga Vemuri},
title = {A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {91},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183120},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs
SN - 1063-9667
SP
EP
A1 - Manish Handa,
A1 - Rajesh Radhakrishnan,
A1 - Madhubanti Mukherjee,
A1 - Ranga Vemuri,
PY - 2003
KW - FPGA
KW - Reconfigurable Computing
KW - Partial Reconfiguration.
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Manish Handa, University of Cincinnati
Rajesh Radhakrishnan, University of Cincinnati
Madhubanti Mukherjee, University of Cincinnati
Ranga Vemuri, University of Cincinnati
In this paper, we propose a methodology for automated mapping of a design onto a partially reconfigurable device. We generate partial bitstream files from behavioral description of the task, that are used to reconfigure the device dynamically. The novelty of this research lies in the application of a Macro Based Synthesis approach that allows elimination of both logic synthesis and technology mapping phases from the synthesis flow. Our methodology provides a significant reduction in compilation time compared to commercial tools.
Index Terms:
FPGA, Reconfigurable Computing, Partial Reconfiguration.
Citation:
Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri, "A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs," vlsid, pp.91, 16th International Conference on VLSI Design, 2003
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