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Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits
New Delhi, India January 04-January 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.118312616th International Conference on VLSI ...
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D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao, "Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits," VLSI Design, International Conference on, pp. 128, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183126,
author = {D. Vinay Kumar and Nihar R. Mohapatra and Mahesh B. Patil and V. Ramgopal Rao},
title = {Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {128},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183126},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits
SN - 1063-9667
SP
EP
A1 - D. Vinay Kumar,
A1 - Nihar R. Mohapatra,
A1 - Mahesh B. Patil,
A1 - V. Ramgopal Rao,
PY - 2003
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
D. Vinay Kumar, Indian Institute of Technology-Bombay
Nihar R. Mohapatra, Indian Institute of Technology-Bombay
Mahesh B. Patil, Indian Institute of Technology-Bombay
V. Ramgopal Rao, Indian Institute of Technology-Bombay
In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluation of circuits directly from device simulation results without going through model parameter extraction.
Citation:
D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao, "Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits," vlsid, pp.128, 16th International Conference on VLSI Design, 2003
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