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Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration
Mumbai, India January 05-January 09
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.126091817th International Conference on VLSI ...
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Anup Savla, The Ohio State University
Jennifer Leonard, The Ohio State University
Arun Ravindran, University of North Carolina at Charlotte
This paper presents an ADC architecture which enhances accuracy of pipelines conversion using digital calibration. The popular 1.5 bit/stage pipeline architecture is adapted to an arbitrary radix structure. Calibration algorithms that estimate gain errors for two comparators in each pipeline stage are developed using this architecture. A low-noise queuing technique which enables calibration to be performed in background without interrupting the ADC input sample stream is presented.
A 12-stage pipeline ADC model is used to demonstrate the effectiveness of calibration algorithms. With 10% error in the interstage gain, calibration improves the accuracy from 5 to 11 bits. Effects of implementation issues such as gain parameter settling, intradie gain variation, and finite word length computation are studied.
Citation:
Anup Savla, Jennifer Leonard, Arun Ravindran, "Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration," vlsid, pp.157, 17th International Conference on VLSI Design, 2004
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