In this paper, we describe split-path domino (SP domino) logic which is capable of high speed due to the magnitude of the charge sharing problem being halved. SP domino logic splits the NMOS stacked transistors used for logic evaluation, in order to reduce charge sharing problem, which has become one of the most critical noise problems in VDSM technology. Furthermore, SP domino logic needs no signal ordering. Dual Vt assignment methodology for SP domino logic was also proposed, in order to provide improved performance with low power consumption overhead. Our experimental results, with several logic gates using 0.18um CMOS technology, showed that the proposed logic provides an improvement in performance of up to 17% compared to the textbook domino circuit, under the same noisy conditions. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.