Design and Implementation of a Parallel Verilog Simulator: PVSim

Mumbai, India January 05-January 09

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260944

17th International Conference on VLSI ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Tun Li Articles by Yang Guo Articles by Si-Kun Li

	ASCII Text	x
	Tun Li, Yang Guo, Si-Kun Li, "Design and Implementation of a Parallel Verilog Simulator: PVSim," VLSI Design, International Conference on, pp. 329, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260944, author = {Tun Li and Yang Guo and Si-Kun Li}, title = {Design and Implementation of a Parallel Verilog Simulator: PVSim}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {329}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260944}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Design and Implementation of a Parallel Verilog Simulator: PVSim SN - 1063-9667 SP EP A1 - Tun Li, A1 - Yang Guo, A1 - Si-Kun Li, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Tun Li, National University of Defense Technology, ChangSha, HuNan, China

Yang Guo, National University of Defense Technology, ChangSha, HuNan, China

Si-Kun Li, National University of Defense Technology, ChangSha, HuNan, China

Parallel HDL simulation is an efficient method to accelerate the verification process of large complex VLSI system design. This paper presents a parallel Verilog simulator - PVSim, which bases on optimistic asynchronous parallel simulation algorithm and MPI library. A new module-based simulation component mapping method is proposed. And an efficient module-based partition algorithm combined with pre-simulation partition algorithm is adopted. This paper introduces the architecture of PVSim, the Verilog component mapping techniques, the distributed simulation cycle arrangement and the circuit partition algorithm in detail. Experimental results show that PVSim can get promising speedup, as well as distributed workload and communication cost across processors.

Citation:

Tun Li, Yang Guo, Si-Kun Li, "Design and Implementation of a Parallel Verilog Simulator: PVSim," vlsid, pp.329, 17th International Conference on VLSI Design, 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.