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Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?m CMOS
Mumbai, India January 05-January 09
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.126095717th International Conference on VLSI ...
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Padmanava Sen, Vipul Garg, Ramesh Garg, Nirmal B Chakrabarti, "Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?m CMOS," VLSI Design, International Conference on, pp. 410, 17th International Conference on VLSI Design, 2004.
 
 
BibTex
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@article{ 10.1109/ICVD.2004.1260957,
author = {Padmanava Sen and Vipul Garg and Ramesh Garg and Nirmal B Chakrabarti},
title = {Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?m CMOS},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2004},
issn = {1063-9667},
pages = {410},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260957},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?m CMOS
SN - 1063-9667
SP
EP
A1 - Padmanava Sen,
A1 - Vipul Garg,
A1 - Ramesh Garg,
A1 - Nirmal B Chakrabarti,
PY - 2004
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Padmanava Sen, Indian Institute of Technology Kharagpur
Vipul Garg, Indian Institute of Technology Kharagpur
Ramesh Garg, Indian Institute of Technology Kharagpur
Nirmal B Chakrabarti, Indian Institute of Technology Kharagpur
This paper presents a step by step design of power amplifiers at 2.4 GHz (for WLAN applications) and on-chip linearization of these amplifiers. CMOS power amplifiers are designed at 2.4 GHz with output power ranging from 30 mW to 100 mW with efficiency varying from 20%-40%. Two or three stages are cascaded according to the gain and efficiency requirements. The topology used for 2.4 GHz amplifier is also verified as a part of an FM transmitter at 900 MHz. All these integrated power amplifiers are not intended to have a very good linearity. At the later part of this work, feed-forward technique is used for linearization of a 2.4 GHz two-stage power amplifier in 0.25 ?m CMOS8 process. The power output of the linear amplifier (in push-pull configuration) is 17 dBm with 20% efficiency. The in-band non-linearity (from two-tone simulations) is given by 3rd order inter-modulation product and is about 40 dBc. For on-chip combining, transformers and baluns are used. All the circuits are simulated using CADENCE tools (ICFB). Inductors, transformers and baluns are designed and simulated using ASITIC tools [1]. The power amplifiers are currently under fabrication in CMOS8 (0.25 ?m) and CMOS9 (0.18 ?m) processes.
Citation:
Padmanava Sen, Vipul Garg, Ramesh Garg, Nirmal B Chakrabarti, "Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?m CMOS," vlsid, pp.410, 17th International Conference on VLSI Design, 2004
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