A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability

Mumbai, India January 05-January 09

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260977

17th International Conference on VLSI ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by S. S. Prasad Articles by Pradip Mandal

	ASCII Text	x
	S. S. Prasad, Pradip Mandal, "A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability," VLSI Design, International Conference on, pp. 551, 17th International Conference on VLSI Design, 2004.

	BibTex	x
	@article{ 10.1109/ICVD.2004.1260977, author = {S. S. Prasad and Pradip Mandal}, title = {A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {551}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260977}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability SN - 1063-9667 SP EP A1 - S. S. Prasad, A1 - Pradip Mandal, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

S. S. Prasad, Alliance Semiconductor (India) Pvt. Ltd.

Pradip Mandal, Alliance Semiconductor (India) Pvt. Ltd.

A new implementation has been proposed for the Beta Multiplier Voltage Reference to improve its performance with regard to process variations. The scope for silicon tunability on the proposed circuit is also discussed. The circuit was implemented in a 0.18? process and was found to have a temperature sensitivity of less than 500 ppm/C in the virgin die without trimming.

Citation:

S. S. Prasad, Pradip Mandal, "A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability," vlsid, pp.551, 17th International Conference on VLSI Design, 2004

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.