Kun Gao, Dinesh P. Mehta,
"Floorplan Classification Algorithms,"
VLSI Design, International Conference on, pp. 975, 17th International Conference on VLSI Design, 2004.
BibTex
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@article{
10.1109/ICVD.2004.1261057, author = {Kun Gao and Dinesh P. Mehta}, title = {Floorplan Classification Algorithms}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2004}, issn = {1063-9667}, pages = {975}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261057}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI Design, International Conference on TI - Floorplan Classification Algorithms SN - 1063-9667 SP EP A1 - Kun Gao, A1 - Dinesh P. Mehta, PY - 2004 KW - null VL - 0 JA - VLSI Design, International Conference on ER -
We present optimal linear time algorithms that determine whether a given general floorplan represented by a q-sequence or twin binary trees is slicing or hierarchical. Experimental results on several benchmarks are presented.
Citation:
Kun Gao, Dinesh P. Mehta, "Floorplan Classification Algorithms," vlsid, pp.975, 17th International Conference on VLSI Design, 2004
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