A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC

Kolkata, India January 03-January 07

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http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.6

18th International Conference on VLSI ...

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	Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey, "A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC," VLSI Design, International Conference on, pp. 319-322, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

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	@article{ 10.1109/ICVD.2005.6, author = {Samiran Halder and Swapna Banerjee and Arindrajit Ghosh and Ravi sankar Prasad and Anirban Chatterjee and Sanjoy Kumar Dey}, title = {A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {319-322}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.6}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

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	TY - CONF JO - VLSI Design, International Conference on TI - A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC SN - 1063-9667 SP319 EP322 A1 - Samiran Halder, A1 - Swapna Banerjee, A1 - Arindrajit Ghosh, A1 - Ravi sankar Prasad, A1 - Anirban Chatterjee, A1 - Sanjoy Kumar Dey, PY - 2005 KW - MOS Analog Circuits KW - Digital to Analog Conversion KW - Mixed Analog -Digital Integrated Circuits KW - Low Power VL - 0 JA - VLSI Design, International Conference on ER -

Samiran Halder, IHP- Germany

Swapna Banerjee, Indian Institute of Technology-Kharagpur

Arindrajit Ghosh, Indian Institute of Technology-Kharagpur

Ravi sankar Prasad, Indian Institute of Technology-Kharagpur

Anirban Chatterjee, Qualcorelogic Ltd Habsiduda

Sanjoy Kumar Dey, Indian Institute of Technology-Kharagpur

This Paper presents a 10 bits 80 MSPS 2.5 V digital-to-analog converter (DAC) using 0.25 micrometer double poly four metal CMOS technology for mixed-signal applications. A segmented current steering architecture is used for this DAC. This architecture gives the most optimized results in terms of speed, resolution, area and power. The DAC can operate at a frequency of 80MHz and above. Total power dissipation is 27.6525 mW with 2.5 V power supply. It achieves differential nonlinearity and integral nonlinearity of ?0.55 LSB and ?0.4 LSB. It occupies an area of 0.185 mm².

Index Terms:

MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power

Citation:

Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey, "A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC," vlsid, pp.319-322, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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