A Combinational Logic Mapper for Actel's SX/AX Family

Kolkata, India January 03-January 07

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http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.8

18th International Conference on VLSI ...

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	Santanu Chattopadhyay, Manas Kumar Dewangan, "A Combinational Logic Mapper for Actel's SX/AX Family," VLSI Design, International Conference on, pp. 669-672, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005.

	BibTex	x
	@article{ 10.1109/ICVD.2005.8, author = {Santanu Chattopadhyay and Manas Kumar Dewangan}, title = {A Combinational Logic Mapper for Actel's SX/AX Family}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2005}, issn = {1063-9667}, pages = {669-672}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2005.8}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Combinational Logic Mapper for Actel's SX/AX Family SN - 1063-9667 SP669 EP672 A1 - Santanu Chattopadhyay, A1 - Manas Kumar Dewangan, PY - 2005 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Santanu Chattopadhyay, Indian Institute of Technology-Guwahati

Manas Kumar Dewangan, Indian Institute of Technology-Guwahati

This paper presents a technology mapper for combinational circuits targeting Actel's SX-A/AX logic module. To the best of our knowledge, this is the first such effort reported in the literature. It exploits the module architecture completely to come up with good mapping solutions. In the absence of similar works, results have been compared with act1 and act2 mappers and found to be encouraging.

Citation:

Santanu Chattopadhyay, Manas Kumar Dewangan, "A Combinational Logic Mapper for Actel's SX/AX Family," vlsid, pp.669-672, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID'05), 2005

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