High-level test generation using physically-induced faults

Princeton, New Jersey April 30-May 03

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512612

13th IEEE VLSI Test Symposium (VTS'95)

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	M.C. Hansen, J.P. Hayes, "High-level test generation using physically-induced faults," VLSI Test Symposium, IEEE, pp. 0020, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512612, author = {M.C. Hansen and J.P. Hayes}, title = {High-level test generation using physically-induced faults}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0020}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512612}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

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	TY - CONF JO - VLSI Test Symposium, IEEE TI - High-level test generation using physically-induced faults SN - 0-8186-7000-2 SP EP A1 - M.C. Hansen, A1 - J.P. Hayes, PY - 1995 KW - fault diagnosis; logic testing; automatic testing; integrated circuit testing; failure analysis; design for testability; high-level test generation; physically-induced faults; industry-standard single stuck-line faults; independent functional faults; functional tests; circuit under test; benchmark circuits; near-minimal size VL - 0 JA - VLSI Test Symposium, IEEE ER -

M.C. Hansen, Advanced Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA

J.P. Hayes, Advanced Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA

Abstract: A high-level fault modeling and testing philosophy is proposed which is aimed at ensuring full detection of low level, physical faults, as well as the industry-standard single stuck-line (SSL) faults. A set of independent functional faults and the corresponding functional tests are derived (induced) from the circuit under test; of particular interest are SSL-induced functional faults or SIFs. We present, for the first time, complete functional circuit models and tests for representative 74X-series and ISCAS-85 benchmark circuits, and apply the proposed methodology to them. These examples demonstrate that functional testing can, with far less effort than conventional method, produce test sets that provide complete coverage of SSL faults in practical circuits. Surprisingly, these test sets are also provably of minimal or near-minimal size.

Index Terms:

fault diagnosis; logic testing; automatic testing; integrated circuit testing; failure analysis; design for testability; high-level test generation; physically-induced faults; industry-standard single stuck-line faults; independent functional faults; functional tests; circuit under test; benchmark circuits; near-minimal size

Citation:

M.C. Hansen, J.P. Hayes, "High-level test generation using physically-induced faults," vts, pp.0020, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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