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A solution for the on-line test of analog ladder filters
Princeton, New Jersey April 30-May 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.51261613th IEEE VLSI Test Symposium (VTS'95)
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D. Vazquez, Dpto. de Diseno Analogico, Univ. de Sevilla, Spain
A. Rueda, Dpto. de Diseno Analogico, Univ. de Sevilla, Spain
J.L. Huertas, Dpto. de Diseno Analogico, Univ. de Sevilla, Spain
Abstract: In this paper we study stability problems associated with the previously developed design for test (DFT) methodology applied to ladder filters. A solution based on simple modification of the basic DFT strategy is proposed which allows on-line testing of ladder filters. A filter example demonstrates the feasibility of the solution.
Index Terms:
analogue integrated circuits; ladder filters; active filters; circuit stability; design for testability; integrated circuit testing; analog ladder filters; stability problems; design for test methodology; on-line testing; solution feasibility; analogue ICs; active filters
Citation:
D. Vazquez, A. Rueda, J.L. Huertas, "A solution for the on-line test of analog ladder filters," vts, pp.0048, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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