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Cyclic stress tests for full scan circuits
Princeton, New Jersey April 30-May 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.51262213th IEEE VLSI Test Symposium (VTS'95)
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V. Dabholkar, S. Chakravarty, J. Najm, J. Patel, "Cyclic stress tests for full scan circuits," VLSI Test Symposium, IEEE, pp. 0089, 13th IEEE VLSI Test Symposium (VTS'95), 1995.
 
 
BibTex
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@article{ 10.1109/VTEST.1995.512622,
author = {V. Dabholkar and S. Chakravarty and J. Najm and J. Patel},
title = {Cyclic stress tests for full scan circuits},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1995},
isbn = {0-8186-7000-2},
pages = {0089},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512622},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Cyclic stress tests for full scan circuits
SN - 0-8186-7000-2
SP
EP
A1 - V. Dabholkar,
A1 - S. Chakravarty,
A1 - J. Najm,
A1 - J. Patel,
PY - 1995
KW - integrated circuit reliability; integrated circuit testing; VLSI; CMOS logic circuits; logic testing; boundary scan testing; cyclic stress tests; full scan circuits; fully testable unpackaged dies; MCMs; burn-in process; cyclic input sequences; stress related problems; ISCAS89 benchmark circuits; monitored burn-in problems; VLSI; IC reliability; CMOS
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
V. Dabholkar, State Univ. of New York, Buffalo, NY, USA
S. Chakravarty, State Univ. of New York, Buffalo, NY, USA
J. Najm, State Univ. of New York, Buffalo, NY, USA
J. Patel, State Univ. of New York, Buffalo, NY, USA
Abstract: To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxonomy of stress related problems for full scan circuits is presented. It is shown that there are efficient ways to compute the sequences for many variations of monitored burn-in problems. Preliminary experimental results on ISCAS89 benchmark circuits are presented.
Index Terms:
integrated circuit reliability; integrated circuit testing; VLSI; CMOS logic circuits; logic testing; boundary scan testing; cyclic stress tests; full scan circuits; fully testable unpackaged dies; MCMs; burn-in process; cyclic input sequences; stress related problems; ISCAS89 benchmark circuits; monitored burn-in problems; VLSI; IC reliability; CMOS
Citation:
V. Dabholkar, S. Chakravarty, J. Najm, J. Patel, "Cyclic stress tests for full scan circuits," vts, pp.0089, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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