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Resynthesis for sequential circuits designed with a specified initial state
Princeton, New Jersey April 30-May 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.51263013th IEEE VLSI Test Symposium (VTS'95)
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H. Yotsuyanagi, S. Kajihara, K. Kinoshita, "Resynthesis for sequential circuits designed with a specified initial state," VLSI Test Symposium, IEEE, pp. 0152, 13th IEEE VLSI Test Symposium (VTS'95), 1995.
 
 
BibTex
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@article{ 10.1109/VTEST.1995.512630,
author = {H. Yotsuyanagi and S. Kajihara and K. Kinoshita},
title = {Resynthesis for sequential circuits designed with a specified initial state},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1995},
isbn = {0-8186-7000-2},
pages = {0152},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512630},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Resynthesis for sequential circuits designed with a specified initial state
SN - 0-8186-7000-2
SP
EP
A1 - H. Yotsuyanagi,
A1 - S. Kajihara,
A1 - K. Kinoshita,
PY - 1995
KW - sequential circuits; logic CAD; circuit optimisation; timing; redundancy; flip-flops; synchronous sequential circuits; specified initial state; retiming method; redundancy removal method; resynthesized circuit; input sequences; flip-flops; logic optimisation
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
H. Yotsuyanagi, Dept. of Appl. Phys., Osaka Univ., Japan
S. Kajihara, Dept. of Appl. Phys., Osaka Univ., Japan
K. Kinoshita, Dept. of Appl. Phys., Osaka Univ., Japan
Abstract: This paper presents a retiming and redundancy removal method for a sequential circuit with a specified initial state so that the resynthesized circuit has a state corresponding to the initial state and gives same behavior for any input sequences of the original circuit. Experimental results show the proposed method can optimize circuits as well as the method which does not consider the specified initial state.
Index Terms:
sequential circuits; logic CAD; circuit optimisation; timing; redundancy; flip-flops; synchronous sequential circuits; specified initial state; retiming method; redundancy removal method; resynthesized circuit; input sequences; flip-flops; logic optimisation
Citation:
H. Yotsuyanagi, S. Kajihara, K. Kinoshita, "Resynthesis for sequential circuits designed with a specified initial state," vts, pp.0152, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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