loading...
Simulation of at-speed tests for stuck-at faults
Princeton, New Jersey April 30-May 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.51264013th IEEE VLSI Test Symposium (VTS'95)
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
T.J. Chakraborty, AT&T Bell Labs., Princeton, NJ, USA
V.D. Agrawal, AT&T Bell Labs., Princeton, NJ, USA
Abstract: We examine the detectability of stuck-at faults when test vectors are applied at the rated speed. In the presence of path delays that are comparable to the clock interval, delayed signal transitions or timing hazards influence the detection of faults. It is, therefore, possible that a stuck-at fault that is detected by a test applied at slow speed, may not be detected with high speed test application. We present a fault simulation method that takes timing effects into account without specific delay modeling. Delay-hazard robust (dh-robust) coverage of a test sequence is defined as the coverage of single stuck-at faults that are guaranteed to be detected irrespective of delays or hazards. For tests generated for slow-speed testing, the dh-robust coverage can be quite low. However, special timing considerations in test generation provide better quality tests, especially for high performance circuits.
Index Terms:
fault diagnosis; logic testing; timing; delays; circuit analysis computing; hazards and race conditions; integrated circuit testing; stuck-at fault detectability; at-speed test simulation; path delays; delayed signal transitions; timing hazards; high speed test; fault simulation method; delay-hazard robust test coverage; timing considerations; high performance circuits
Citation:
T.J. Chakraborty, V.D. Agrawal, "Simulation of at-speed tests for stuck-at faults," vts, pp.0216, 13th IEEE VLSI Test Symposium (VTS'95), 1995
Usage of this product signifies your acceptance of the Terms of Use.