Reliability evaluation of combinational logic circuits by symbolic simulation

Princeton, New Jersey April 30-May 03

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512643

13th IEEE VLSI Test Symposium (VTS'95)

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by A. Bogliolo Articles by M. Damiani Articles by P. Olivo Articles by B. Ricco

	ASCII Text	x
	A. Bogliolo, M. Damiani, P. Olivo, B. Ricco, "Reliability evaluation of combinational logic circuits by symbolic simulation," VLSI Test Symposium, IEEE, pp. 0235, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512643, author = {A. Bogliolo and M. Damiani and P. Olivo and B. Ricco}, title = {Reliability evaluation of combinational logic circuits by symbolic simulation}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0235}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512643}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Reliability evaluation of combinational logic circuits by symbolic simulation SN - 0-8186-7000-2 SP EP A1 - A. Bogliolo, A1 - M. Damiani, A1 - P. Olivo, A1 - B. Ricco, PY - 1995 KW - integrated circuit reliability; combinational circuits; circuit analysis computing; digital simulation; logic CAD; VLSI; reliability evaluation; VLSI; mcnc benchmark circuits; fault-tolerant combinational logic circuits; circuit functionality; fault indicators; control variables; BDD-based symbolic simulation; undetectable multiple faults VL - 0 JA - VLSI Test Symposium, IEEE ER -

A. Bogliolo, DEIS, Bologna Univ., Italy

M. Damiani, DEIS, Bologna Univ., Italy

P. Olivo, DEIS, Bologna Univ., Italy

B. Ricco, DEIS, Bologna Univ., Italy

Abstract: This paper presents new algorithms for evaluating the reliability of fault-tolerant combinational logic circuits. In order to model the effects of multiple faults on circuit functionality, we use fault indicators as control variables. We use BDD-based symbolic simulation to avoid the explicit enumeration of faults. We present experimental results on fault-tolerant implementations of several mcnc benchmark circuits. They show that undetectable multiple faults have a large impact on the reliability of fault-tolerant circuits.

Index Terms:

integrated circuit reliability; combinational circuits; circuit analysis computing; digital simulation; logic CAD; VLSI; reliability evaluation; VLSI; mcnc benchmark circuits; fault-tolerant combinational logic circuits; circuit functionality; fault indicators; control variables; BDD-based symbolic simulation; undetectable multiple faults

Citation:

A. Bogliolo, M. Damiani, P. Olivo, B. Ricco, "Reliability evaluation of combinational logic circuits by symbolic simulation," vts, pp.0235, 13th IEEE VLSI Test Symposium (VTS'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.