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Improving the efficiency of error identification via signature analysis
Princeton, New Jersey April 30-May 03
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.51264413th IEEE VLSI Test Symposium (VTS'95)
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C.E. Stroud, T.R. Damarla, "Improving the efficiency of error identification via signature analysis," VLSI Test Symposium, IEEE, pp. 0244, 13th IEEE VLSI Test Symposium (VTS'95), 1995.
 
 
BibTex
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@article{ 10.1109/VTEST.1995.512644,
author = {C.E. Stroud and T.R. Damarla},
title = {Improving the efficiency of error identification via signature analysis},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1995},
isbn = {0-8186-7000-2},
pages = {0244},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512644},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Improving the efficiency of error identification via signature analysis
SN - 0-8186-7000-2
SP
EP
A1 - C.E. Stroud,
A1 - T.R. Damarla,
PY - 1995
KW - VLSI; built-in self test; integrated circuit testing; fault diagnosis; logic testing; error identification; signature analysis; single bit errors; input polynomial; characteristic polynomial; least common multiple; diagnostic aliasing; multiple bit errors; nonprimitive polynomials; BIST; VLSI
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
C.E. Stroud, Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
T.R. Damarla, Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Abstract: Efficient identification of all single bit errors in the input polynomial to signature analysis registers is achieved by using characteristic polynomial f(x)=f/sub a/(x)f/sub b/(x) where f/sub a/(x) and f/sub b/(x) have different degrees and are of the form f/sub n/(x)=x/sup n/+x/sup n-1/+1. The input polynomial must be of degree >lcm(ord(f/sub a/(x)), ord(f/sub b/(x))), where lcm denotes the least common multiple. Diagnostic aliasing for multiple bit errors is reduced by using non-primitive polynomials for f/sub a/(x) and/or f/sub b/(x).
Index Terms:
VLSI; built-in self test; integrated circuit testing; fault diagnosis; logic testing; error identification; signature analysis; single bit errors; input polynomial; characteristic polynomial; least common multiple; diagnostic aliasing; multiple bit errors; nonprimitive polynomials; BIST; VLSI
Citation:
C.E. Stroud, T.R. Damarla, "Improving the efficiency of error identification via signature analysis," vts, pp.0244, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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