A partial scan methodology for testing self-timed circuits

Princeton, New Jersey April 30-May 03

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512650

13th IEEE VLSI Test Symposium (VTS'95)

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	A. Khoche, E. Brunvand, "A partial scan methodology for testing self-timed circuits," VLSI Test Symposium, IEEE, pp. 0283, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

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	@article{ 10.1109/VTEST.1995.512650, author = {A. Khoche and E. Brunvand}, title = {A partial scan methodology for testing self-timed circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0283}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512650}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

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	TY - CONF JO - VLSI Test Symposium, IEEE TI - A partial scan methodology for testing self-timed circuits SN - 0-8186-7000-2 SP EP A1 - A. Khoche, A1 - E. Brunvand, PY - 1995 KW - asynchronous circuits; logic testing; design for testability; logic design; boundary scan testing; integrated circuit testing; integrated logic circuits; partial scan methodology; self-timed circuits; control section testing; macromodule based circuits; stuck-at faults; fault coverage; sequential network VL - 0 JA - VLSI Test Symposium, IEEE ER -

A. Khoche, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

E. Brunvand, Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA

Abstract: This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable.

Index Terms:

asynchronous circuits; logic testing; design for testability; logic design; boundary scan testing; integrated circuit testing; integrated logic circuits; partial scan methodology; self-timed circuits; control section testing; macromodule based circuits; stuck-at faults; fault coverage; sequential network

Citation:

A. Khoche, E. Brunvand, "A partial scan methodology for testing self-timed circuits," vts, pp.0283, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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