Reducing test application time in scan design schemes

Princeton, New Jersey April 30-May 03

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512662

13th IEEE VLSI Test Symposium (VTS'95)

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	B. Vinnakota, N.J. Stessman, "Reducing test application time in scan design schemes," VLSI Test Symposium, IEEE, pp. 0367, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

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	@article{ 10.1109/VTEST.1995.512662, author = {B. Vinnakota and N.J. Stessman}, title = {Reducing test application time in scan design schemes}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0367}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512662}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

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	TY - CONF JO - VLSI Test Symposium, IEEE TI - Reducing test application time in scan design schemes SN - 0-8186-7000-2 SP EP A1 - B. Vinnakota, A1 - N.J. Stessman, PY - 1995 KW - boundary scan testing; fault diagnosis; logic testing; sequential circuits; automatic testing; graph theory; correlation methods; test application time; scan design schemes; sequential circuits; computationally intractable problem; heuristic techniques; fault simulation; test vector correlation; fault coverage; test times VL - 0 JA - VLSI Test Symposium, IEEE ER -

B. Vinnakota, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

N.J. Stessman, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

Abstract: We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without affecting fault coverage. Our methods can be used to process a test set after test generation is complete. They lead to a substantial reduction in test times.

Index Terms:

boundary scan testing; fault diagnosis; logic testing; sequential circuits; automatic testing; graph theory; correlation methods; test application time; scan design schemes; sequential circuits; computationally intractable problem; heuristic techniques; fault simulation; test vector correlation; fault coverage; test times

Citation:

B. Vinnakota, N.J. Stessman, "Reducing test application time in scan design schemes," vts, pp.0367, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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