Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages

Princeton, NJ April 28-May 01

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510879

14th IEEE VLSI Test Symposium (VTS '96)

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by A. Chatterjee Articles by R. Jayabharathi Articles by P. Pant Articles by J.A. Abraham

	ASCII Text	x
	A. Chatterjee, R. Jayabharathi, P. Pant, J.A. Abraham, "Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages," VLSI Test Symposium, IEEE, pp. 354, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510879, author = {A. Chatterjee and R. Jayabharathi and P. Pant and J.A. Abraham}, title = {Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {354}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510879}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages SN - 0-8186-7304-4 SP EP A1 - A. Chatterjee, A1 - R. Jayabharathi, A1 - P. Pant, A1 - J.A. Abraham, PY - 1996 KW - combinational circuits; fault diagnosis; logic testing; waveform analysis; automatic testing; integrated circuit testing; redundancy; nonrobust tests; stuck-fault detection; signal waveform analysis; signal waveform integration; combinational circuits; fault coverage; test application time; detectability; redundant faults; directed random test generation techniques VL - 0 JA - VLSI Test Symposium, IEEE ER -

A. Chatterjee, Georgia Inst. of Technol., Atlanta, GA, USA

R. Jayabharathi, Georgia Inst. of Technol., Atlanta, GA, USA

P. Pant, Georgia Inst. of Technol., Atlanta, GA, USA

J.A. Abraham, Georgia Inst. of Technol., Atlanta, GA, USA

In this paper we propose to use an output signal waveform analysis method called signal waveform integration for detection of stuck-at failures in combinational circuits. Non-robust tests are applied at-speed or faster to achieve high fault coverage, low test application time and detectability of redundant faults using directed random test generation techniques.

Index Terms:

combinational circuits; fault diagnosis; logic testing; waveform analysis; automatic testing; integrated circuit testing; redundancy; nonrobust tests; stuck-fault detection; signal waveform analysis; signal waveform integration; combinational circuits; fault coverage; test application time; detectability; redundant faults; directed random test generation techniques

Citation:

A. Chatterjee, R. Jayabharathi, P. Pant, J.A. Abraham, "Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages," vts, pp.354, 14th IEEE VLSI Test Symposium (VTS '96), 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.