Design and performance of CMOS TSPC cells for high speed pseudo random testing

Princeton, NJ April 28-May 01

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510880

14th IEEE VLSI Test Symposium (VTS '96)

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	ASCII Text	x
	M. Soufi, S. Rochon, Y. Savaria, B. Kaminska, "Design and performance of CMOS TSPC cells for high speed pseudo random testing," VLSI Test Symposium, IEEE, pp. 368, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510880, author = {M. Soufi and S. Rochon and Y. Savaria and B. Kaminska}, title = {Design and performance of CMOS TSPC cells for high speed pseudo random testing}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {368}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510880}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Design and performance of CMOS TSPC cells for high speed pseudo random testing SN - 0-8186-7304-4 SP EP A1 - M. Soufi, A1 - S. Rochon, A1 - Y. Savaria, A1 - B. Kaminska, PY - 1996 KW - CMOS logic circuits; clocks; cellular arrays; integrated circuit testing; logic testing; built-in self test; SPICE; circuit analysis computing; circuit layout CAD; logic CAD; integrated circuit layout; CMOS TSPC cells; high speed pseudo random testing; test methodology; built-in self-test scheme; HSpice simulations; netlists; layout; functionally equivalent logic block; untestable faults; true single phase clocking VL - 0 JA - VLSI Test Symposium, IEEE ER -

M. Soufi, Ecole Polytech. de Montreal, Que., Canada

S. Rochon, Ecole Polytech. de Montreal, Que., Canada

Y. Savaria, Ecole Polytech. de Montreal, Que., Canada

B. Kaminska, Ecole Polytech. de Montreal, Que., Canada

In this paper the problem of testing high speed CMOS circuits is considered. A test methodology based on a Built-in Self-Test scheme adapted to TSPC circuits is proposed. We show through HSpice simulations on netlists extracted from layout that this scheme can operate at more than 580 MHz. Moreover, an efficient solution to the problem of redesigning an easily testable functionally equivalent logic block to eliminate hard to test and untestable faults in TSPC circuits is introduced.

Index Terms:

CMOS logic circuits; clocks; cellular arrays; integrated circuit testing; logic testing; built-in self test; SPICE; circuit analysis computing; circuit layout CAD; logic CAD; integrated circuit layout; CMOS TSPC cells; high speed pseudo random testing; test methodology; built-in self-test scheme; HSpice simulations; netlists; layout; functionally equivalent logic block; untestable faults; true single phase clocking

Citation:

M. Soufi, S. Rochon, Y. Savaria, B. Kaminska, "Design and performance of CMOS TSPC cells for high speed pseudo random testing," vts, pp.368, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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