A fault model for switch-level simulation of gate-to-drain shorts

Princeton, NJ April 28-May 01

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510887

14th IEEE VLSI Test Symposium (VTS '96)

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	P. Dahlgren, P. Liden, "A fault model for switch-level simulation of gate-to-drain shorts," VLSI Test Symposium, IEEE, pp. 414, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510887, author = {P. Dahlgren and P. Liden}, title = {A fault model for switch-level simulation of gate-to-drain shorts}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {414}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510887}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A fault model for switch-level simulation of gate-to-drain shorts SN - 0-8186-7304-4 SP EP A1 - P. Dahlgren, A1 - P. Liden, PY - 1996 KW - integrated circuit modelling; fault diagnosis; fault model; switch-level simulation; gate-to-drain shorts; algorithm; transistor-level bridging faults; network primitive; subnetworks; iteration; electrical-level analysis VL - 0 JA - VLSI Test Symposium, IEEE ER -

P. Dahlgren, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden

P. Liden, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden

An efficient algorithm for analyzing a subset of transistor-level bridging faults is proposed. The complex analogue behavior of gate-to-drain shorts is handled using a network primitive into which the fault injected transistor is mapped. The resistances of the surrounding subnetworks obtained from a linear switch-level model are used together with a simple iteration scheme to predict the voltage at the shortened nodes. Fault simulation experiments were conducted and the algorithm shows good agreement with electrical-level analysis.

Index Terms:

integrated circuit modelling; fault diagnosis; fault model; switch-level simulation; gate-to-drain shorts; algorithm; transistor-level bridging faults; network primitive; subnetworks; iteration; electrical-level analysis

Citation:

P. Dahlgren, P. Liden, "A fault model for switch-level simulation of gate-to-drain shorts," vts, pp.414, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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