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An unexpected factor in testing for CMOS opens: the die surface
Princeton, NJ April 28-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.51088814th IEEE VLSI Test Symposium (VTS '96)
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H. Konuk, F.J. Ferguson, "An unexpected factor in testing for CMOS opens: the die surface," VLSI Test Symposium, IEEE, pp. 422, 14th IEEE VLSI Test Symposium (VTS '96), 1996.
 
 
BibTex
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@article{ 10.1109/VTEST.1996.510888,
author = {H. Konuk and F.J. Ferguson},
title = {An unexpected factor in testing for CMOS opens: the die surface},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1996},
isbn = {0-8186-7304-4},
pages = {422},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510888},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - An unexpected factor in testing for CMOS opens: the die surface
SN - 0-8186-7304-4
SP
EP
A1 - H. Konuk,
A1 - F.J. Ferguson,
PY - 1996
KW - CMOS integrated circuits; integrated circuit testing; integrated circuit modelling; VLSI; surface phenomena; electric charge; CMOS opens; die surface; RC interconnect; circuit model; HSPICE simulations; trapped charge; floating gates
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
H. Konuk, California Design Center, Hewlett-Packard Co., CA, USA
F.J. Ferguson, California Design Center, Hewlett-Packard Co., CA, USA
We present the experimental evidence, for the first time, that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a floating wire created by a CMOS open. We present a circuit model for this effect verified with HSPICE simulations. A detailed analysis of potential mechanisms behind this phenomenon is provided. We also present our measurement results for the trapped charge deposited on floating gates during fabrication.
Index Terms:
CMOS integrated circuits; integrated circuit testing; integrated circuit modelling; VLSI; surface phenomena; electric charge; CMOS opens; die surface; RC interconnect; circuit model; HSPICE simulations; trapped charge; floating gates
Citation:
H. Konuk, F.J. Ferguson, "An unexpected factor in testing for CMOS opens: the die surface," vts, pp.422, 14th IEEE VLSI Test Symposium (VTS '96), 1996
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