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Using fault sampling to compute I/sub DDQ/ diagnostic test sets
Monterey, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.59944415th IEEE VLSI Test Symposium (VTS'97)
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Yiming Gong, S. Chakravarty, "Using fault sampling to compute I/sub DDQ/ diagnostic test sets," VLSI Test Symposium, IEEE, pp. 74, 15th IEEE VLSI Test Symposium (VTS'97), 1997.
 
 
BibTex
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@article{ 10.1109/VTEST.1997.599444,
author = {Yiming Gong and S. Chakravarty},
title = {Using fault sampling to compute I/sub DDQ/ diagnostic test sets},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1997},
isbn = {0-8186-7810-0},
pages = {74},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.599444},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Using fault sampling to compute I/sub DDQ/ diagnostic test sets
SN - 0-8186-7810-0
SP
EP
A1 - Yiming Gong,
A1 - S. Chakravarty,
PY - 1997
KW - combinational circuits; fault sampling; IDDQ diagnostic test set generation; bridging faults; combinational circuit
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Yiming Gong, Quickturn Syst. Inc., Mountain View, CA, USA
S. Chakravarty, Quickturn Syst. Inc., Mountain View, CA, USA
A diagnostic test generation system for computing I/sub DQQ/ diagnostic test sets for bridging faults in combinational circuits is presented. The system uses fault sampling. Experimental results presented show that fault sampling is a very effective method for computing diagnostic test sets, especially when the number of target faults is very large.
Index Terms:
combinational circuits; fault sampling; IDDQ diagnostic test set generation; bridging faults; combinational circuit
Citation:
Yiming Gong, S. Chakravarty, "Using fault sampling to compute I/sub DDQ/ diagnostic test sets," vts, pp.74, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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