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On the Fault Coverage of Interconnect Diagnosis
Monterey, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.59945015th IEEE VLSI Test Symposium (VTS'97)
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X.T. Chen, Texas A & M University
F.J. Meyer, Texas A & M University
F. Lombardi, Texas A & M University
This paper deals with the inverse problem (namely, diagnosability) for diagnosing bridge faults in interconnects. Given a test set (T) and the layout of an interconnect, the diagnosability problem consists of establishing the probability (coverage) of diagnosing (detection and/or location) all faults and to identify the undiagnosable faults (if any). It is proved that this process is equivalent of checking each edge in the adjacency graph representation of the layout using the tests in T (either parallel, or sequential test vectors). Different algorithms are given for diagnosis and detection.
Index Terms:
interconnect testing, diagnose, adjacency graph
Citation:
X.T. Chen, F.J. Meyer, F. Lombardi, "On the Fault Coverage of Interconnect Diagnosis," vts, pp.101, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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