Structured Design-For-Testability (DFT) employs automated Design-Rules-Checking (DRC) to ensure a design is testable and test patterns can be produced using Automated Test Pattern Generation (ATPG). Central to DRC are ATPG-related clock rules. This paper defines a robust set of clock rules and their implementation for scan designs. It then extends clock-rule-violation detection beyond test requirements, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools. Results on a large microprocessor design show the applicability of ATPG-based timing verification.
Index Terms:
computer testing; ATPG; clock rules checking; complex scan designs; structured DFT; automated design-rules-checking; robust set of rules; clock-rule-violation detection; fast clock verification; large microprocessor design; timing verification; topological circuit analysis; zero delay; user controlled verification; capture ability; race conditions; port contention; cone tracing; equivalent sources
Citation:
P. Wohl, J. Waicukauski, "Using ATPG for clock rules checking in complex scan designs," vts, pp.130, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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