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Functional test pattern generation for CMOS operational amplifier
Monterey, California April 27-May 01
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.60028715th IEEE VLSI Test Symposium (VTS'97)
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Soon Jyh Chang, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Jwu E Chen, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
In this paper, the optimum functional patterns for CMOS operational amplifier are proposed based on an analysis to find the maximum difference between the good circuit and the faulty circuit for a CMOS operational amplifier. The theoretical and simulation results show that the derived test patterns do give the maximum difference at the output even when the circuit has a "soft" fault. The results have also been applied to generate test patterns for a programmable gain/loss mixed signal circuit.
Index Terms:
CMOS analogue integrated circuits; functional test pattern generation; CMOS operational amplifier; programmable gain/loss mixed signal circuit; op amp testing; IC testing
Citation:
Soon Jyh Chang, Chung Len Lee, Jwu E Chen, "Functional test pattern generation for CMOS operational amplifier," vts, pp.267, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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