Random pattern testability of memory control logic

Monterey, California April 27-May 01

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http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600317

15th IEEE VLSI Test Symposium (VTS'97)

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	ASCII Text	x
	J. Savir, "Random pattern testability of memory control logic," VLSI Test Symposium, IEEE, pp. 399, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600317, author = {J. Savir}, title = {Random pattern testability of memory control logic}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {399}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600317}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Random pattern testability of memory control logic SN - 0-8186-7810-0 SP EP A1 - J. Savir, PY - 1997 KW - integrated memory circuits; random pattern testability; fault detection; embedded memory control logic; exposure probability; signal probability VL - 0 JA - VLSI Test Symposium, IEEE ER -

J. Savir, Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

Index Terms:

integrated memory circuits; random pattern testability; fault detection; embedded memory control logic; exposure probability; signal probability

Citation:

J. Savir, "Random pattern testability of memory control logic," vts, pp.399, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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