O.V. Maiuri, W.R. Moore,
"2.1 Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm,"
VLSI Test Symposium, IEEE, pp. 22, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670844, author = {O.V. Maiuri and W.R. Moore}, title = {2.1 Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {22}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670844}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI Test Symposium, IEEE TI - 2.1 Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm SN - 1093-0167 SP EP A1 - O.V. Maiuri, A1 - W.R. Moore, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
O.V. Maiuri, W.R. Moore, "2.1 Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm," vts, pp.22, 16th IEEE VLSI Test Symposium, 1998
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