M. Ishida, D.S. Ha, T. Yamaguchi,
"4.1 COMPACT: A Hybrid Method for Compressing Test Data,"
VLSI Test Symposium, IEEE, pp. 62, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670850, author = {M. Ishida and D.S. Ha and T. Yamaguchi}, title = {4.1 COMPACT: A Hybrid Method for Compressing Test Data}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {62}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670850}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - VLSI Test Symposium, IEEE TI - 4.1 COMPACT: A Hybrid Method for Compressing Test Data SN - 1093-0167 SP EP A1 - M. Ishida, A1 - D.S. Ha, A1 - T. Yamaguchi, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb