K. Zarrineh, S.J. Upadhyaya, P. Shephard Iii,
"5.3 Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips,"
VLSI Test Symposium, IEEE, pp. 98, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670855, author = {K. Zarrineh and S.J. Upadhyaya and P. Shephard Iii}, title = {5.3 Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {98}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670855}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI Test Symposium, IEEE TI - 5.3 Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips SN - 1093-0167 SP EP A1 - K. Zarrineh, A1 - S.J. Upadhyaya, A1 - P. Shephard Iii, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
K. Zarrineh, S.J. Upadhyaya, P. Shephard Iii, "5.3 Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips," vts, pp.98, 16th IEEE VLSI Test Symposium, 1998
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