M.W. Tian, C.-J.R. Shi,
"7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation,"
VLSI Test Symposium, IEEE, pp. 126, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670859, author = {M.W. Tian and C.-J.R. Shi}, title = {7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {126}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670859}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI Test Symposium, IEEE TI - 7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation SN - 1093-0167 SP EP A1 - M.W. Tian, A1 - C.-J.R. Shi, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
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