S. Tani, M. Teramoto, T. Fukazawa, K. Matsuhiro,
"9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation,"
VLSI Test Symposium, IEEE, pp. 188, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670867, author = {S. Tani and M. Teramoto and T. Fukazawa and K. Matsuhiro}, title = {9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {188}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670867}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - VLSI Test Symposium, IEEE TI - 9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation SN - 1093-0167 SP EP A1 - S. Tani, A1 - M. Teramoto, A1 - T. Fukazawa, A1 - K. Matsuhiro, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
S. Tani, M. Teramoto, T. Fukazawa, K. Matsuhiro, "9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation," vts, pp.188, 16th IEEE VLSI Test Symposium, 1998
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb