D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz,
"11.1 High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor,"
VLSI Test Symposium, IEEE, pp. 234, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670873, author = {D. Heidel and S. Dhong and P. Hofstee and M. Immediato and K. Nowka and J. Silberman and K. Stawiasz}, title = {11.1 High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {234}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670873}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
x
TY - CONF JO - VLSI Test Symposium, IEEE TI - 11.1 High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor SN - 1093-0167 SP EP A1 - D. Heidel, A1 - S. Dhong, A1 - P. Hofstee, A1 - M. Immediato, A1 - K. Nowka, A1 - J. Silberman, A1 - K. Stawiasz, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silberman, K. Stawiasz, "11.1 High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor," vts, pp.234, 16th IEEE VLSI Test Symposium, 1998
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb