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11.2 Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing
Monterey, California April 26-April 30
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.67087516th IEEE VLSI Test Symposium
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Citation:
I.T. Sylla, M. Slamani, B. Kaminska, F.M. Hossein, P. Vincent, "11.2 Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing," vts, pp.239, 16th IEEE VLSI Test Symposium, 1998
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