M.L. Flottes, R. Pires, B. Rouzeyre, L. Volpe,
"15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach,"
VLSI Test Symposium, IEEE, pp. 332, 16th IEEE VLSI Test Symposium, 1998.
BibTex
x
@article{
10.1109/VTEST.1998.670887, author = {M.L. Flottes and R. Pires and B. Rouzeyre and L. Volpe}, title = {15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1998}, issn = {1093-0167}, pages = {332}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670887}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - VLSI Test Symposium, IEEE TI - 15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach SN - 1093-0167 SP EP A1 - M.L. Flottes, A1 - R. Pires, A1 - B. Rouzeyre, A1 - L. Volpe, PY - 1998 VL - 0 JA - VLSI Test Symposium, IEEE ER -
M.L. Flottes, R. Pires, B. Rouzeyre, L. Volpe, "15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach," vts, pp.332, 16th IEEE VLSI Test Symposium, 1998
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