Foreword

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Steering Committee

pp. xv

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Advisory Board

pp. xvii

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Program Committee

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Test Technology Technical Committee

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pp. xix

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Reviewers

pp. xxiii

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1997 Best Paper Award

pp. xxviii

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1997 Best Panel Award

pp. xxix

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Overview of Tutorials

pp. xxx

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Towards a Global Networked Society

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Invited Keynote Address

pp. xxxx

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1.1 Designing a Testable System on a Chip

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Session 1: Core and System on Chip Test: Moderators: Bernard Courtois, TIMA

pp. 2

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1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit

D. Bhattacharya

pp. 8

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1.3 Parallelism in Structural Fault Testing of Embedded Cores

M. Nourani

C. Papachristou

pp. 15

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2.1 Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm

Session 2: Testing Deep Submicron Circuits: Moderators: Vishwani D. Agrawal, Lucent Technologies

O.V. Maiuri

W.R. Moore

pp. 22

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2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores

pp. 28

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2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits

K.T. Lee

C. Nordquist

J.A. Abraham

pp. 34

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3.1 Fault Detection and Diagnosis of Interconnects of Random Access Memories

Session 3: Diagnosis and Validation: Moderators: Wayne Needham, Intel

J. Zhao

F.J. Meyer

F. Lombardi

pp. 42

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3.2 A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis

K. Shigeta

T. Ishiyama

pp. 48

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3.3 Performance Test Case Generation for Microprocessors

P. Bose

pp. 54

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4.1 COMPACT: A Hybrid Method for Compressing Test Data

Session 4: BIST 1: Moderators: Melvin A. Breuer, University of Southern California

M. Ishida

D.S. Ha

T. Yamaguchi

pp. 62

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4.2 Synthesis of Zero-Aliasing Elementary-Tree Space Compactors

B. Pouya

N.A. Touba

pp. 70

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4.3 Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions

A.P. Stroele

pp. 78

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5.1 Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan

Session 5: Scan & Boundary Scan: Moderators: Gordon Robinson, Credence Systems

A. Majumdar

M. Komoda

T. Ayres

pp. 86

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5.2 Self-Timed Boundary-Scan Cells for Multi-Chip Module Test

pp. 92

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5.3 Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips

K. Zarrineh

S.J. Upadhyaya

P. Shephard Iii

pp. 98

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6.1 IDDQ Testing of Opens in CMOS SRAMs

Session 6: IDDQ and VLV Test: Moderators: Thomas W. Williams, Synopsys

V.H. Champac

J. Castillejos

J. Figueras

pp. 106

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6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults

T. Shinogi

T. Hayashi

pp. 112

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6.3 Experimental Results for IDDQ and VLV Testing

pp. 118

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7.1 Nonlinear Analog DC Fault Simulation by One-Step Relaxation

Session 7: Analog Test: Moderators: Laroussi Bouzaida, SGS Thomson

M.W. Tian

C.-J.R. Shi

pp. 126

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7.2 Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements

P.N. Variyam

A. Chatterjee

pp. 132

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7.3 Effect of Noise on Analog Circuit Testing

M.K. Iyer

M.L. Bushnell

pp. 138

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7.4 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits

H. Yoon

P. Variyam

A. Chatterjee

N. Nagi

pp. 145

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8.1 Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model

Session 8: Sequential Test and Redundancy Removal: Moderators: Jim Aylor, University of Virginia

pp. 152

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8.2 On Synchronizing Sequences and Test Sequence Partitioning

I. Pomeranz

S.M. Reddy

pp. 158

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8.3 On Removing Redundant Faults in Synchronous Sequential Circuits

X. Lin

I. Pomeranz

S.M. Reddy

pp. 168

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8.4 Undetectable Fault Removal of Sequential Circuits Based on Unreachable States

H. Yotsuyanagi

K. Kinoshita

pp. 176

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Analysis of Failures in Deep Submicron SRAM Cells

Embedded Tutorial 1

Pinaki Mazumder

pp. 184

9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation

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Session 9: Delay Fault Test: Moderators: Kenneth Butler, Texas Instruments

S. Tani

M. Teramoto

T. Fukazawa

K. Matsuhiro

pp. 188

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9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy

S. Majumder

V.D. Agrawal

M.L. Bushnell

pp. 194

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9.3 Improving Path Delay Fault Testability by Path Removal

U. Sparmann

L. Köller

pp. 200

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10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion

Session 10: BIST 2: Moderators: Shianling Wu, Lucent Technologies

G. Parthasarathy

M.L. Bushnell

pp. 210

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10.2 Design of Phase Shifters for BIST Applications

J. Rajski

J. Tyszer

pp. 218

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10.3 Distributed Generation of Weighted Random Patterns

J. Savir

pp. 225

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11.1 High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor

Session 11: Testing High-Speed Circuits: Moderators: Robert Aitken, Hewlett-Packard

pp. 234

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11.2 Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing

pp. 239

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11.3 Mixed Signal DFT at GHz Frequencies

R. Mason

S. Ma

pp. 245

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12.1 Using Verification Technology for Validation Coverage Analysis and Test Generation

Session 12: Validation/Verification: Moderators: Barry Johnson, University of Virginia

D. Moundanos

J.A. Abraham

pp. 254

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12.2 On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays

L.-C. Wang

M.S. Abadir

J. Zeng

pp. 260

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12.3 A Novel Routing Algorithm for MCM Substrate Verification Using Single-Ended Probe

R. Yan

B.C. Kim

pp. 266

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13.1 A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric

Session 13: Defect Level Test: Moderators: Wojciech Maly, Carnegie Mellon University

D. Williams

F.J. Ferguson

T. Larrabee

pp. 274

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13.2 Sampling Techniques of Non-Equally Probable Faults in VLSI Systems

F.M. Gonçalves

J.P. Teixeira

pp. 283

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13.3 Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage

I. Pomeranz

S.M. Reddy

pp. 289

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14.1 Fast Self-Recovering Controllers

Session 14: Concurrent Checking & Fault Tolerance: Moderators: David Keezer, Georgia Tech

A. Hertwig

S. Hellebrand

H.-J. Wunderlich

pp. 296

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14.2 Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits

C.E. Stroud

J.K. Tannehill Jr.

pp. 303

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14.3 Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes

D. Das

N.A. Touba

pp. 309

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Test Reuse at System Level

Panel 1: Moderator/Coordinator: Y. Zorian, LogicVision

pp. 318

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Panel and Embedded Tutorial 2: Moderator/Coordinator: Bernard Courtois, TIMA

pp. 320

Validation and Test Problems for Cross Talk Noise

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Embedded Tutorial 3: Coordinator: Tim Cheng, University of California, Santa Barbara

Presenters: Sandip Gupta

Craig Gleason

pp. 322

15.1 A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing

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Session 15: Scan Techniques: Moderators: Yashwant Malaiya, Colorado State University

E.S. Sogomonyan

A.D. Singh

M. Goessel

pp. 324

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15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach

pp. 332

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15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation

H.-C. Liang

C.L. Lee

J.E. Chen

pp. 341

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16.1 Novel Single and Double Output TSC Berger Code Checkers

Session 16: On-Line Testing: Moderators: Cecilia Metra, University of Bologna

X. Kavousianos

D. Nikolos

pp. 348

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16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST

M. Gössel M. Seurin

E. Sogomonyan

pp. 354

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16.3 Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under Check

A. Kuchukyan

pp. 362

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17.1 Design-For-Testability for Switched-Current Circuits

Session 17: Analog/Mixed Signal Test and DFT: Moderators: Rene Segers, Philips

pp. 370

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17.2 A Design for Testability Study on a High Performance Automatic Gain Control Circuit

pp. 376

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17.3 Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling

R. de Vries

A.J.E.M. Janssen

pp. 386

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18.1 A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags

Session 18: Memory Test: Moderators: David Broster, European Commission

S.M. Al-Harbi

S.K. Gupta

pp. 394

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18.2 Fault Models and Tests for Two-Port Memories

A.J. van de Goor

S. Hamdioui

pp. 401

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18.3 An Approach to Modeling and Testing Memories and Its Application to CAMs

P.R. Sidorowicz

J.A. Brzozowski

pp. 411

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19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets

Session 19: BIST 3: Moderators: Kewal Saluja, University of Wisconsin

V. Iyengar

K. Chakrabarty

B.T. Murray

pp. 418

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19.2 On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits

pp. 424

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19.3 Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators

B.F. Cockburn

A.L.-C. Kwong

pp. 430

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20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults

Session 20: New ATPG Techniques: Moderators: Rajesh Galivanche, Intel

D. Karayiannis

S. Tragoudas

pp. 440

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20.2 New Techniques for Deterministic Test Pattern Generation

I. Hamzaoglu

J.H. Patel

pp. 446

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20.3 A Test Pattern Generation Methodology for Low-Power Consumption

pp. 453

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Best Methods for At-Speed Testing?

Panel 3: Moderator: Theo Powell, Texas Instruments

Sreejit Chakravarty

Theo Powell

pp. 460

An Introduction to RF Testing: Device, Method and System

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Embedded Tutorial 4: Coordinator: Bozena Kaminska, OPMAXX

Presenter: Jeffrey S. Kasten

pp. 462

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Where We Might Stumble with Embedded-System Test

Panel 4: Moderator/Coordinator: Fidel Muradali, Hewlett-Packard

Co-Coordinator: Keerthi Heragu

Texas Instruments

pp. 470

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Author Index

pp. 471

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